cpldfit:  version I.34                              Xilinx Inc.
                                  Fitter Report
Design Name: speckey                             Date: 11- 3-2006, 11:50PM
Device Used: XC9572-15-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
52 /72  ( 72%) 183 /360  ( 51%) 121/144 ( 84%)   46 /72  ( 64%) 18 /34  ( 53%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          16/18       32/36       32          53/90       0/ 9
FB2          16/18       22/36       22          48/90       0/ 9
FB3          16/18       32/36       32          53/90       1/ 8
FB4           4/18       35/36       35          29/90       4/ 8
             -----       -----                   -----       -----     
             52/72      121/144                 183/360      5/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   13          13    |  I/O              :    16      28
Output        :    5           5    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     1       2
GCK           :    0           0    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     18          18

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 52 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:897 - Unable to map all desired signals into function block, FB4.
   Buffering output signal z80_db<4> to allow all signals assigned to this
   function block to be placed.
*************************  Summary of Mapped Logic  ************************

** 5 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
z80_db<0>           9     18    FB3_17  22   I/O     O       LOW  SLOW 
z80_db<1>           9     18    FB4_2   24   I/O     O       LOW  SLOW 
z80_db<2>           9     18    FB4_5   25   I/O     O       LOW  SLOW 
z80_db<3>           9     18    FB4_8   26   I/O     O       LOW  SLOW 
z80_db<4>           2     3     FB4_9   27   I/O     O       LOW  SLOW 

** 47 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
kb_data<9>          3     10    FB1_3   LOW  RESET
kb_data<4>          3     10    FB1_4   LOW  RESET
kb_data<39>         3     10    FB1_5   LOW  RESET
kb_data<34>         3     10    FB1_6   LOW  RESET
kb_data<29>         3     10    FB1_7   LOW  RESET
kb_data<26>         3     10    FB1_8   LOW  RESET
kb_data<24>         3     10    FB1_9   LOW  RESET
kb_data<23>         3     10    FB1_10  LOW  RESET
kb_data<22>         3     10    FB1_11  LOW  RESET
kb_data<21>         3     10    FB1_12  LOW  RESET
kb_data<1>          3     10    FB1_13  LOW  RESET
kb_data<19>         3     10    FB1_14  LOW  RESET
kb_data<18>         3     10    FB1_15  LOW  RESET
kb_data<17>         3     10    FB1_16  LOW  RESET
kb_addr<4>          3     6     FB1_17  LOW  RESET
z80_db<4>_BUFR      8     16    FB1_18  LOW  
kb_data<8>          3     10    FB2_3   LOW  RESET
kb_data<7>          3     10    FB2_4   LOW  RESET
kb_data<6>          3     10    FB2_5   LOW  RESET
kb_data<3>          3     10    FB2_6   LOW  RESET
kb_data<38>         3     10    FB2_7   LOW  RESET
kb_data<37>         3     10    FB2_8   LOW  RESET
kb_data<36>         3     10    FB2_9   LOW  RESET
kb_data<33>         3     10    FB2_10  LOW  RESET
kb_data<32>         3     10    FB2_11  LOW  RESET
kb_data<31>         3     10    FB2_12  LOW  RESET
kb_data<2>          3     10    FB2_13  LOW  RESET
kb_data<28>         3     10    FB2_14  LOW  RESET
kb_data<27>         3     10    FB2_15  LOW  RESET
kb_addr<3>          3     5     FB2_16  LOW  RESET
kb_addr<2>          3     4     FB2_17  LOW  RESET
kb_addr<1>          3     3     FB2_18  LOW  RESET
kb_addr<0>          2     2     FB3_1   LOW  RESET
kb_data<5>          3     10    FB3_4   LOW  RESET
kb_data<35>         3     10    FB3_5   LOW  RESET
kb_data<30>         3     10    FB3_6   LOW  RESET
kb_data<25>         3     10    FB3_7   LOW  RESET
kb_data<20>         3     10    FB3_8   LOW  RESET
kb_data<16>         3     10    FB3_9   LOW  RESET
kb_data<15>         3     10    FB3_10  LOW  RESET

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
kb_data<14>         3     10    FB3_11  LOW  RESET
kb_data<13>         3     10    FB3_12  LOW  RESET
kb_data<12>         3     10    FB3_13  LOW  RESET
kb_data<11>         3     10    FB3_14  LOW  RESET
kb_data<10>         3     10    FB3_15  LOW  RESET
kb_data<0>          3     10    FB3_16  LOW  RESET
kb_addr<5>          3     7     FB3_18  LOW  RESET

** 13 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
addr<2>             FB2_2   35   I/O     I
addr<1>             FB2_5   36   I/O     I
mcu_reset           FB2_6   37   I/O     I
addr<3>             FB2_8   38   I/O     I
mcu_kbd             FB2_9   39   GSR/I/O I
mcu_clk             FB2_11  40   GTS/I/O I
addr<7>             FB3_8   13   I/O     I
addr<6>             FB3_9   14   I/O     I
addr<4>             FB3_11  18   I/O     I
addr<5>             FB3_14  19   I/O     I
iorq_ULA            FB4_11  28   I/O     I
addr<0>             FB4_15  33   I/O     I
z80_rd              FB4_17  34   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\2   3     FB1_1         (b)     (b)
(unused)              0       0     0   5     FB1_2   1     I/O     
kb_data<9>            3       0     0   2     FB1_3         (b)     (b)
kb_data<4>            3       0     0   2     FB1_4         (b)     (b)
kb_data<39>           3       0     0   2     FB1_5   2     I/O     (b)
kb_data<34>           3       0     0   2     FB1_6   3     I/O     (b)
kb_data<29>           3       0     0   2     FB1_7         (b)     (b)
kb_data<26>           3       0     0   2     FB1_8   4     I/O     (b)
kb_data<24>           3       0     0   2     FB1_9   5     GCK/I/O (b)
kb_data<23>           3       0     0   2     FB1_10        (b)     (b)
kb_data<22>           3       0     0   2     FB1_11  6     GCK/I/O (b)
kb_data<21>           3       0     0   2     FB1_12        (b)     (b)
kb_data<1>            3       0     0   2     FB1_13        (b)     (b)
kb_data<19>           3       0     0   2     FB1_14  7     GCK/I/O (b)
kb_data<18>           3       0     0   2     FB1_15  8     I/O     (b)
kb_data<17>           3       0     0   2     FB1_16        (b)     (b)
kb_addr<4>            3       0   \/1   1     FB1_17  9     I/O     (b)
z80_db<4>_BUFR        8       3<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: addr<0>           12: kb_addr<3>        23: kb_data<24>.LFBK 
  2: addr<1>           13: kb_addr<4>.LFBK   24: kb_data<26>.LFBK 
  3: addr<2>           14: kb_addr<5>        25: kb_data<29>.LFBK 
  4: addr<3>           15: kb_data<14>       26: kb_data<34>.LFBK 
  5: addr<4>           16: kb_data<17>.LFBK  27: kb_data<39>.LFBK 
  6: addr<5>           17: kb_data<18>.LFBK  28: kb_data<4>.LFBK 
  7: addr<6>           18: kb_data<19>.LFBK  29: kb_data<9>.LFBK 
  8: addr<7>           19: kb_data<1>.LFBK   30: mcu_clk 
  9: kb_addr<0>        20: kb_data<21>.LFBK  31: mcu_kbd 
 10: kb_addr<1>        21: kb_data<22>.LFBK  32: mcu_reset 
 11: kb_addr<2>        22: kb_data<23>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
kb_data<9>           ........XXXXXX..............XXXX........ 10      10
kb_data<4>           ........XXXXXX.............X.XXX........ 10      10
kb_data<39>          ........XXXXXX............X..XXX........ 10      10
kb_data<34>          ........XXXXXX...........X...XXX........ 10      10
kb_data<29>          ........XXXXXX..........X....XXX........ 10      10
kb_data<26>          ........XXXXXX.........X.....XXX........ 10      10
kb_data<24>          ........XXXXXX........X......XXX........ 10      10
kb_data<23>          ........XXXXXX.......X.......XXX........ 10      10
kb_data<22>          ........XXXXXX......X........XXX........ 10      10
kb_data<21>          ........XXXXXX.....X.........XXX........ 10      10
kb_data<1>           ........XXXXXX....X..........XXX........ 10      10
kb_data<19>          ........XXXXXX...X...........XXX........ 10      10
kb_data<18>          ........XXXXXX..X............XXX........ 10      10
kb_data<17>          ........XXXXXX.X.............XXX........ 10      10
kb_addr<4>           ........XXXX.................X.X........ 6       6
z80_db<4>_BUFR       XXXXXXXX......X..X....X.XXXXX........... 16      16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               22/14
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   35    I/O     I
kb_data<8>            3       0     0   2     FB2_3         (b)     (b)
kb_data<7>            3       0     0   2     FB2_4         (b)     (b)
kb_data<6>            3       0     0   2     FB2_5   36    I/O     I
kb_data<3>            3       0     0   2     FB2_6   37    I/O     I
kb_data<38>           3       0     0   2     FB2_7         (b)     (b)
kb_data<37>           3       0     0   2     FB2_8   38    I/O     I
kb_data<36>           3       0     0   2     FB2_9   39    GSR/I/O I
kb_data<33>           3       0     0   2     FB2_10        (b)     (b)
kb_data<32>           3       0     0   2     FB2_11  40    GTS/I/O I
kb_data<31>           3       0     0   2     FB2_12        (b)     (b)
kb_data<2>            3       0     0   2     FB2_13        (b)     (b)
kb_data<28>           3       0     0   2     FB2_14  42    GTS/I/O (b)
kb_data<27>           3       0     0   2     FB2_15  43    I/O     (b)
kb_addr<3>            3       0     0   2     FB2_16        (b)     (b)
kb_addr<2>            3       0     0   2     FB2_17  44    I/O     (b)
kb_addr<1>            3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: kb_addr<0>         9: kb_data<2>.LFBK   16: kb_data<3>.LFBK 
  2: kb_addr<1>.LFBK   10: kb_data<31>.LFBK  17: kb_data<6>.LFBK 
  3: kb_addr<2>.LFBK   11: kb_data<32>.LFBK  18: kb_data<7>.LFBK 
  4: kb_addr<3>.LFBK   12: kb_data<33>.LFBK  19: kb_data<8>.LFBK 
  5: kb_addr<4>        13: kb_data<36>.LFBK  20: mcu_clk 
  6: kb_addr<5>        14: kb_data<37>.LFBK  21: mcu_kbd 
  7: kb_data<27>.LFBK  15: kb_data<38>.LFBK  22: mcu_reset 
  8: kb_data<28>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
kb_data<8>           XXXXXX............XXXX.................. 10      10
kb_data<7>           XXXXXX...........X.XXX.................. 10      10
kb_data<6>           XXXXXX..........X..XXX.................. 10      10
kb_data<3>           XXXXXX.........X...XXX.................. 10      10
kb_data<38>          XXXXXX........X....XXX.................. 10      10
kb_data<37>          XXXXXX.......X.....XXX.................. 10      10
kb_data<36>          XXXXXX......X......XXX.................. 10      10
kb_data<33>          XXXXXX.....X.......XXX.................. 10      10
kb_data<32>          XXXXXX....X........XXX.................. 10      10
kb_data<31>          XXXXXX...X.........XXX.................. 10      10
kb_data<2>           XXXXXX..X..........XXX.................. 10      10
kb_data<28>          XXXXXX.X...........XXX.................. 10      10
kb_data<27>          XXXXXXX............XXX.................. 10      10
kb_addr<3>           XXX................X.X.................. 5       5
kb_addr<2>           XX.................X.X.................. 4       4
kb_addr<1>           X..................X.X.................. 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
kb_addr<0>            2       0     0   3     FB3_1         (b)     (b)
(unused)              0       0     0   5     FB3_2   11    I/O     
(unused)              0       0     0   5     FB3_3         (b)     
kb_data<5>            3       0     0   2     FB3_4         (b)     (b)
kb_data<35>           3       0     0   2     FB3_5   12    I/O     (b)
kb_data<30>           3       0     0   2     FB3_6         (b)     (b)
kb_data<25>           3       0     0   2     FB3_7         (b)     (b)
kb_data<20>           3       0     0   2     FB3_8   13    I/O     I
kb_data<16>           3       0     0   2     FB3_9   14    I/O     I
kb_data<15>           3       0     0   2     FB3_10        (b)     (b)
kb_data<14>           3       0     0   2     FB3_11  18    I/O     I
kb_data<13>           3       0     0   2     FB3_12        (b)     (b)
kb_data<12>           3       0     0   2     FB3_13        (b)     (b)
kb_data<11>           3       0     0   2     FB3_14  19    I/O     I
kb_data<10>           3       0     0   2     FB3_15  20    I/O     (b)
kb_data<0>            3       0   \/2   0     FB3_16        (b)     (b)
z80_db<0>             9       4<-   0   0     FB3_17  22    I/O     O
kb_addr<5>            3       0   /\2   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: addr<0>           12: kb_addr<2>        23: kb_data<16>.LFBK 
  2: addr<1>           13: kb_addr<3>        24: kb_data<20>.LFBK 
  3: addr<2>           14: kb_addr<4>        25: kb_data<25>.LFBK 
  4: addr<3>           15: kb_addr<5>.LFBK   26: kb_data<30>.LFBK 
  5: addr<4>           16: kb_data<0>.LFBK   27: kb_data<35>.LFBK 
  6: addr<5>           17: kb_data<10>.LFBK  28: kb_data<5>.LFBK 
  7: addr<6>           18: kb_data<11>.LFBK  29: mcu_clk 
  8: addr<7>           19: kb_data<12>.LFBK  30: mcu_kbd 
  9: iorq_ULA          20: kb_data<13>.LFBK  31: mcu_reset 
 10: kb_addr<0>.LFBK   21: kb_data<14>.LFBK  32: z80_rd 
 11: kb_addr<1>        22: kb_data<15>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
kb_addr<0>           ............................X.X......... 2       2
kb_data<5>           .........XXXXXX............XXXX......... 10      10
kb_data<35>          .........XXXXXX...........X.XXX......... 10      10
kb_data<30>          .........XXXXXX..........X..XXX......... 10      10
kb_data<25>          .........XXXXXX.........X...XXX......... 10      10
kb_data<20>          .........XXXXXX........X....XXX......... 10      10
kb_data<16>          .........XXXXXX.......X.....XXX......... 10      10
kb_data<15>          .........XXXXXX......X......XXX......... 10      10
kb_data<14>          .........XXXXXX.....X.......XXX......... 10      10
kb_data<13>          .........XXXXXX....X........XXX......... 10      10
kb_data<12>          .........XXXXXX...X.........XXX......... 10      10
kb_data<11>          .........XXXXXX..X..........XXX......... 10      10
kb_data<10>          .........XXXXXX.X...........XXX......... 10      10
kb_data<0>           .........XXXXXXX............XXX......... 10      10
z80_db<0>            XXXXXXXXX......XX....X.XXXXX...X........ 18      18
kb_addr<5>           .........XXXXX..............X.X......... 7       7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               35/1
Number of signals used by logic mapping into function block:  35
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/2   3     FB4_1         (b)     (b)
z80_db<1>             9       4<-   0   0     FB4_2   24    I/O     O
(unused)              0       0   /\2   3     FB4_3         (b)     (b)
(unused)              0       0   \/2   3     FB4_4         (b)     (b)
z80_db<2>             9       4<-   0   0     FB4_5   25    I/O     O
(unused)              0       0   /\2   3     FB4_6         (b)     (b)
(unused)              0       0   \/3   2     FB4_7         (b)     (b)
z80_db<3>             9       4<-   0   0     FB4_8   26    I/O     O
z80_db<4>             2       0   /\1   2     FB4_9   27    I/O     O
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  28    I/O     I
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  29    I/O     
(unused)              0       0     0   5     FB4_15  33    I/O     I
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  34    I/O     I
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block
  1: addr<0>           13: kb_data<16>       25: kb_data<32> 
  2: addr<1>           14: kb_data<17>       26: kb_data<33> 
  3: addr<2>           15: kb_data<18>       27: kb_data<36> 
  4: addr<3>           16: kb_data<1>        28: kb_data<37> 
  5: addr<4>           17: kb_data<21>       29: kb_data<38> 
  6: addr<5>           18: kb_data<22>       30: kb_data<3> 
  7: addr<6>           19: kb_data<23>       31: kb_data<6> 
  8: addr<7>           20: kb_data<26>       32: kb_data<7> 
  9: iorq_ULA          21: kb_data<27>       33: kb_data<8> 
 10: kb_data<11>       22: kb_data<28>       34: z80_db<4>_BUFR 
 11: kb_data<12>       23: kb_data<2>        35: z80_rd 
 12: kb_data<13>       24: kb_data<31>      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
z80_db<1>            XXXXXXXXXX..X..XX..X...X..X...X...X..... 18      18
z80_db<2>            XXXXXXXXX.X..X...X..X.X.X..X...X..X..... 18      18
z80_db<3>            XXXXXXXXX..X..X...X..X...X..XX..X.X..... 18      18
z80_db<4>            ........X........................XX..... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********













FTCPE_kb_addr0: FTCPE port map (kb_addr(0),'1',NOT mcu_clk,mcu_reset,'0');

FTCPE_kb_addr1: FTCPE port map (kb_addr(1),kb_addr(0),NOT mcu_clk,mcu_reset,'0');

FTCPE_kb_addr2: FTCPE port map (kb_addr(2),kb_addr_T(2),NOT mcu_clk,mcu_reset,'0');
kb_addr_T(2) <= (kb_addr(0) AND kb_addr(1).LFBK);

FTCPE_kb_addr3: FTCPE port map (kb_addr(3),kb_addr_T(3),NOT mcu_clk,mcu_reset,'0');
kb_addr_T(3) <= (kb_addr(0) AND kb_addr(1).LFBK AND kb_addr(2).LFBK);

FTCPE_kb_addr4: FTCPE port map (kb_addr(4),kb_addr_T(4),NOT mcu_clk,mcu_reset,'0');
kb_addr_T(4) <= (kb_addr(0) AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2));

FTCPE_kb_addr5: FTCPE port map (kb_addr(5),kb_addr_T(5),NOT mcu_clk,mcu_reset,'0');
kb_addr_T(5) <= (kb_addr(1) AND kb_addr(3) AND kb_addr(2) AND 
	kb_addr(4) AND kb_addr(0).LFBK);

FTCPE_kb_data0: FTCPE port map (kb_data(0),kb_data_T(0),mcu_clk,'0','0');
kb_data_T(0) <= ((NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND NOT kb_data(0).LFBK AND 
	NOT kb_addr(0).LFBK AND NOT kb_addr(5).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND kb_data(0).LFBK AND 
	NOT kb_addr(0).LFBK AND NOT kb_addr(5).LFBK));

FTCPE_kb_data1: FTCPE port map (kb_data(1),kb_data_T(1),mcu_clk,'0','0');
kb_data_T(1) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	NOT kb_addr(4).LFBK AND NOT kb_data(1).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	NOT kb_addr(4).LFBK AND kb_data(1).LFBK));

FTCPE_kb_data2: FTCPE port map (kb_data(2),kb_data_T(2),mcu_clk,'0','0');
kb_data_T(2) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(2).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(2).LFBK));

FTCPE_kb_data3: FTCPE port map (kb_data(3),kb_data_T(3),mcu_clk,'0','0');
kb_data_T(3) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(3).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(3).LFBK));

FTCPE_kb_data4: FTCPE port map (kb_data(4),kb_data_T(4),mcu_clk,'0','0');
kb_data_T(4) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	NOT kb_addr(4).LFBK AND NOT kb_data(4).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	NOT kb_addr(4).LFBK AND kb_data(4).LFBK));

FTCPE_kb_data5: FTCPE port map (kb_data(5),kb_data_T(5),mcu_clk,'0','0');
kb_data_T(5) <= ((NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(5).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(5).LFBK));

FTCPE_kb_data6: FTCPE port map (kb_data(6),kb_data_T(6),mcu_clk,'0','0');
kb_data_T(6) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(6).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(6).LFBK));

FTCPE_kb_data7: FTCPE port map (kb_data(7),kb_data_T(7),mcu_clk,'0','0');
kb_data_T(7) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(7).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(7).LFBK));

FTCPE_kb_data8: FTCPE port map (kb_data(8),kb_data_T(8),mcu_clk,'0','0');
kb_data_T(8) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND NOT kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND NOT kb_data(8).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND NOT kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND kb_data(8).LFBK));

FTCPE_kb_data9: FTCPE port map (kb_data(9),kb_data_T(9),mcu_clk,'0','0');
kb_data_T(9) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	NOT kb_addr(4).LFBK AND NOT kb_data(9).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	NOT kb_addr(4).LFBK AND kb_data(9).LFBK));

FTCPE_kb_data10: FTCPE port map (kb_data(10),kb_data_T(10),mcu_clk,'0','0');
kb_data_T(10) <= ((NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(10).LFBK)
	OR (NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(10).LFBK));

FTCPE_kb_data11: FTCPE port map (kb_data(11),kb_data_T(11),mcu_clk,'0','0');
kb_data_T(11) <= ((NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(11).LFBK)
	OR (NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(11).LFBK));

FTCPE_kb_data12: FTCPE port map (kb_data(12),kb_data_T(12),mcu_clk,'0','0');
kb_data_T(12) <= ((NOT mcu_reset AND NOT kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(12).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(12).LFBK));

FTCPE_kb_data13: FTCPE port map (kb_data(13),kb_data_T(13),mcu_clk,'0','0');
kb_data_T(13) <= ((NOT mcu_reset AND NOT kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(13).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(13).LFBK));

FTCPE_kb_data14: FTCPE port map (kb_data(14),kb_data_T(14),mcu_clk,'0','0');
kb_data_T(14) <= ((NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(14).LFBK)
	OR (NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(14).LFBK));

FTCPE_kb_data15: FTCPE port map (kb_data(15),kb_data_T(15),mcu_clk,'0','0');
kb_data_T(15) <= ((NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND NOT kb_data(15).LFBK AND 
	kb_addr(0).LFBK AND NOT kb_addr(5).LFBK)
	OR (NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND kb_data(15).LFBK AND 
	kb_addr(0).LFBK AND NOT kb_addr(5).LFBK));

FTCPE_kb_data16: FTCPE port map (kb_data(16),kb_data_T(16),mcu_clk,'0','0');
kb_data_T(16) <= ((NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	NOT kb_addr(2) AND kb_addr(4) AND mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND NOT kb_data(16).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	NOT kb_addr(2) AND kb_addr(4) AND NOT mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_addr(5).LFBK AND kb_data(16).LFBK));

FTCPE_kb_data17: FTCPE port map (kb_data(17),kb_data_T(17),mcu_clk,'0','0');
kb_data_T(17) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	kb_addr(4).LFBK AND NOT kb_data(17).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_addr(4).LFBK AND kb_data(17).LFBK));

FTCPE_kb_data18: FTCPE port map (kb_data(18),kb_data_T(18),mcu_clk,'0','0');
kb_data_T(18) <= ((NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	kb_addr(4).LFBK AND NOT kb_data(18).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_addr(4).LFBK AND kb_data(18).LFBK));

FTCPE_kb_data19: FTCPE port map (kb_data(19),kb_data_T(19),mcu_clk,'0','0');
kb_data_T(19) <= ((NOT mcu_reset AND kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	NOT kb_data(19).LFBK AND kb_addr(4).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_data(19).LFBK AND kb_addr(4).LFBK));

FTCPE_kb_data20: FTCPE port map (kb_data(20),kb_data_T(20),mcu_clk,'0','0');
kb_data_T(20) <= ((NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	kb_addr(2) AND kb_addr(4) AND mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_data(20).LFBK AND NOT kb_addr(5).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND NOT kb_addr(3) AND 
	kb_addr(2) AND kb_addr(4) AND NOT mcu_kbd AND NOT kb_addr(0).LFBK AND 
	kb_data(20).LFBK AND NOT kb_addr(5).LFBK));

FTCPE_kb_data21: FTCPE port map (kb_data(21),kb_data_T(21),mcu_clk,'0','0');
kb_data_T(21) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	kb_addr(4).LFBK AND NOT kb_data(21).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_addr(4).LFBK AND kb_data(21).LFBK));

FTCPE_kb_data22: FTCPE port map (kb_data(22),kb_data_T(22),mcu_clk,'0','0');
kb_data_T(22) <= ((NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	kb_addr(4).LFBK AND NOT kb_data(22).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_addr(4).LFBK AND kb_data(22).LFBK));

FTCPE_kb_data23: FTCPE port map (kb_data(23),kb_data_T(23),mcu_clk,'0','0');
kb_data_T(23) <= ((NOT mcu_reset AND kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	kb_addr(4).LFBK AND NOT kb_data(23).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_addr(4).LFBK AND kb_data(23).LFBK));

FTCPE_kb_data24: FTCPE port map (kb_data(24),kb_data_T(24),mcu_clk,'0','0');
kb_data_T(24) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(1) AND 
	kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	NOT kb_data(24).LFBK AND kb_addr(4).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(1) AND 
	kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_data(24).LFBK AND kb_addr(4).LFBK));

FTCPE_kb_data25: FTCPE port map (kb_data(25),kb_data_T(25),mcu_clk,'0','0');
kb_data_T(25) <= ((NOT mcu_reset AND NOT kb_addr(1) AND kb_addr(3) AND 
	NOT kb_addr(2) AND kb_addr(4) AND mcu_kbd AND NOT kb_data(25).LFBK AND 
	kb_addr(0).LFBK AND NOT kb_addr(5).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(1) AND kb_addr(3) AND 
	NOT kb_addr(2) AND kb_addr(4) AND NOT mcu_kbd AND kb_data(25).LFBK AND 
	kb_addr(0).LFBK AND NOT kb_addr(5).LFBK));

FTCPE_kb_data26: FTCPE port map (kb_data(26),kb_data_T(26),mcu_clk,'0','0');
kb_data_T(26) <= ((NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	kb_addr(4).LFBK AND NOT kb_data(26).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	kb_addr(3) AND NOT kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_addr(4).LFBK AND kb_data(26).LFBK));

FTCPE_kb_data27: FTCPE port map (kb_data(27),kb_data_T(27),mcu_clk,'0','0');
kb_data_T(27) <= ((NOT mcu_reset AND kb_addr(0) AND kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND NOT kb_data(27).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND kb_data(27).LFBK));

FTCPE_kb_data28: FTCPE port map (kb_data(28),kb_data_T(28),mcu_clk,'0','0');
kb_data_T(28) <= ((NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND NOT kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND NOT kb_data(28).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND NOT kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND kb_data(28).LFBK));

FTCPE_kb_data29: FTCPE port map (kb_data(29),kb_data_T(29),mcu_clk,'0','0');
kb_data_T(29) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND mcu_kbd AND 
	NOT kb_data(29).LFBK AND kb_addr(4).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(1) AND 
	kb_addr(3) AND kb_addr(2) AND NOT kb_addr(5) AND NOT mcu_kbd AND 
	kb_data(29).LFBK AND kb_addr(4).LFBK));

FTCPE_kb_data30: FTCPE port map (kb_data(30),kb_data_T(30),mcu_clk,'0','0');
kb_data_T(30) <= ((NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND kb_addr(4) AND mcu_kbd AND NOT kb_addr(0).LFBK AND 
	NOT kb_data(30).LFBK AND NOT kb_addr(5).LFBK)
	OR (NOT mcu_reset AND kb_addr(1) AND kb_addr(3) AND 
	kb_addr(2) AND kb_addr(4) AND NOT mcu_kbd AND NOT kb_addr(0).LFBK AND 
	kb_data(30).LFBK AND NOT kb_addr(5).LFBK));

FTCPE_kb_data31: FTCPE port map (kb_data(31),kb_data_T(31),mcu_clk,'0','0');
kb_data_T(31) <= ((NOT mcu_reset AND kb_addr(0) AND kb_addr(4) AND 
	NOT kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND NOT kb_data(31).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND kb_addr(4) AND 
	NOT kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	kb_addr(3).LFBK AND kb_data(31).LFBK));

FTCPE_kb_data32: FTCPE port map (kb_data(32),kb_data_T(32),mcu_clk,'0','0');
kb_data_T(32) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND mcu_kbd AND NOT kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(32).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND NOT mcu_kbd AND NOT kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(32).LFBK));

FTCPE_kb_data33: FTCPE port map (kb_data(33),kb_data_T(33),mcu_clk,'0','0');
kb_data_T(33) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND mcu_kbd AND NOT kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(33).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND NOT mcu_kbd AND NOT kb_addr(1).LFBK AND NOT kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(33).LFBK));

FTCPE_kb_data34: FTCPE port map (kb_data(34),kb_data_T(34),mcu_clk,'0','0');
kb_data_T(34) <= ((NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND kb_addr(5) AND mcu_kbd AND 
	NOT kb_data(34).LFBK AND NOT kb_addr(4).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND NOT kb_addr(2) AND kb_addr(5) AND NOT mcu_kbd AND 
	kb_data(34).LFBK AND NOT kb_addr(4).LFBK));

FTCPE_kb_data35: FTCPE port map (kb_data(35),kb_data_T(35),mcu_clk,'0','0');
kb_data_T(35) <= ((NOT mcu_reset AND kb_addr(1) AND NOT kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND mcu_kbd AND NOT kb_data(35).LFBK AND 
	kb_addr(0).LFBK AND kb_addr(5).LFBK)
	OR (NOT mcu_reset AND kb_addr(1) AND NOT kb_addr(3) AND 
	NOT kb_addr(2) AND NOT kb_addr(4) AND NOT mcu_kbd AND kb_data(35).LFBK AND 
	kb_addr(0).LFBK AND kb_addr(5).LFBK));

FTCPE_kb_data36: FTCPE port map (kb_data(36),kb_data_T(36),mcu_clk,'0','0');
kb_data_T(36) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND mcu_kbd AND NOT kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(36).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND NOT mcu_kbd AND NOT kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(36).LFBK));

FTCPE_kb_data37: FTCPE port map (kb_data(37),kb_data_T(37),mcu_clk,'0','0');
kb_data_T(37) <= ((NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND mcu_kbd AND NOT kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(37).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND NOT mcu_kbd AND NOT kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(37).LFBK));

FTCPE_kb_data38: FTCPE port map (kb_data(38),kb_data_T(38),mcu_clk,'0','0');
kb_data_T(38) <= ((NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND NOT kb_data(38).LFBK)
	OR (NOT mcu_reset AND NOT kb_addr(0) AND NOT kb_addr(4) AND 
	kb_addr(5) AND NOT mcu_kbd AND kb_addr(1).LFBK AND kb_addr(2).LFBK AND 
	NOT kb_addr(3).LFBK AND kb_data(38).LFBK));

FTCPE_kb_data39: FTCPE port map (kb_data(39),kb_data_T(39),mcu_clk,'0','0');
kb_data_T(39) <= ((NOT mcu_reset AND kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND kb_addr(5) AND mcu_kbd AND 
	NOT kb_data(39).LFBK AND NOT kb_addr(4).LFBK)
	OR (NOT mcu_reset AND kb_addr(0) AND kb_addr(1) AND 
	NOT kb_addr(3) AND kb_addr(2) AND kb_addr(5) AND NOT mcu_kbd AND 
	kb_data(39).LFBK AND NOT kb_addr(4).LFBK));


z80_db_I(0) <= NOT (((kb_data(0).EXP)
	OR (kb_addr(5).EXP)
	OR (NOT addr(3) AND kb_data(15).LFBK)
	OR (NOT addr(5) AND kb_data(25).LFBK)
	OR (NOT addr(7) AND kb_data(35).LFBK)
	OR (NOT addr(0) AND kb_data(0).LFBK)));
z80_db(0) <= z80_db_I(0) when z80_db_OE(0) = '1' else 'Z';
z80_db_OE(0) <= (NOT z80_rd AND NOT iorq_ULA);


z80_db_I(1) <= NOT (((EXP1_.EXP)
	OR (EXP2_.EXP)
	OR (kb_data(26) AND NOT addr(5))
	OR (kb_data(31) AND NOT addr(6))
	OR (kb_data(36) AND NOT addr(7))
	OR (kb_data(6) AND NOT addr(1))));
z80_db(1) <= z80_db_I(1) when z80_db_OE(1) = '1' else 'Z';
z80_db_OE(1) <= (NOT z80_rd AND NOT iorq_ULA);


z80_db_I(2) <= NOT (((EXP3_.EXP)
	OR (EXP4_.EXP)
	OR (kb_data(12) AND NOT addr(2))
	OR (kb_data(17) AND NOT addr(3))
	OR (kb_data(22) AND NOT addr(4))
	OR (kb_data(2) AND NOT addr(0))));
z80_db(2) <= z80_db_I(2) when z80_db_OE(2) = '1' else 'Z';
z80_db_OE(2) <= (NOT z80_rd AND NOT iorq_ULA);


z80_db_I(3) <= NOT (((EXP5_.EXP)
	OR (_6_.EXP)
	OR (kb_data(13) AND NOT addr(2))
	OR (kb_data(18) AND NOT addr(3))
	OR (kb_data(23) AND NOT addr(4))
	OR (kb_data(28) AND NOT addr(5))));
z80_db(3) <= z80_db_I(3) when z80_db_OE(3) = '1' else 'Z';
z80_db_OE(3) <= (NOT z80_rd AND NOT iorq_ULA);


z80_db_I(4) <= z80_db(4)_BUFR;
z80_db(4) <= z80_db_I(4) when z80_db_OE(4) = '1' else 'Z';
z80_db_OE(4) <= (NOT z80_rd AND NOT iorq_ULA);


z80_db(4)_BUFR <= NOT (((EXP0_.EXP)
	OR (kb_addr(4).EXP)
	OR (kb_data(14) AND NOT addr(2))
	OR (NOT addr(3) AND kb_data(19).LFBK)
	OR (NOT addr(4) AND kb_data(24).LFBK)
	OR (NOT addr(5) AND kb_data(29).LFBK)
	OR (NOT addr(6) AND kb_data(34).LFBK)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-15-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572-15-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              23 GND                           
  2 TIE                              24 z80_db<1>                     
  3 TIE                              25 z80_db<2>                     
  4 TIE                              26 z80_db<3>                     
  5 TIE                              27 z80_db<4>                     
  6 TIE                              28 iorq_ULA                      
  7 TIE                              29 TIE                           
  8 TIE                              30 TDO                           
  9 TIE                              31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 addr<0>                       
 12 TIE                              34 z80_rd                        
 13 addr<7>                          35 addr<2>                       
 14 addr<6>                          36 addr<1>                       
 15 TDI                              37 mcu_reset                     
 16 TMS                              38 addr<3>                       
 17 TCK                              39 mcu_kbd                       
 18 addr<4>                          40 mcu_clk                       
 19 addr<5>                          41 VCC                           
 20 TIE                              42 TIE                           
 21 VCC                              43 TIE                           
 22 z80_db<0>                        44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-15-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : LOW
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 50