Implementing this into a CPLDBased on the features, at the very minimum it needs
So it needs at least a 64 register device, and that is without any
extra logic. |
VHDL sourceJust the VHDL source code for the LETA replacement | ||||
Notes about the implementationThe CPLD was fitted so unused pins were pulled to ground, macrocells were in low-power mode and programmable slew rate was slow. It was built using Xilinx webpack ise 9.1 and no Xilinx specific features were used, so it should be portable to other architectures. |
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Carrier PCBHaving programable pins on the CPLD allowed me to arrange the routing
so it could be fitted easily onto a single sided PCB, with just two jumper
wires.
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Carrier
PCB - board & schematic | ||||
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Click for the BIG picture | ||||
Testing ! |
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For testing I did a quick check by plugging it into the test board on
page 1. Then into a couple of different PCB.s.
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With Rampart an additional socket is required to lift the carrier board just above the 68000 that sits very tightly to the bottom of the Leta. Sockets. | ||||
And that's all there is too it ! |
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